269 lines
7.3 KiB
ArmAsm
269 lines
7.3 KiB
ArmAsm
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/********************************** (C) COPYRIGHT *******************************
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* File Name : startup_CH59x.s
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* Author : WCH
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* Version : V1.0.1
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* Date : 2023/10/25
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* Description : CH592 FreeRTOS启动文件
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*********************************************************************************
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* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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.section .init,"ax",@progbits
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.global _start
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.align 1
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_start:
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j handle_reset
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.section .vector,"ax",@progbits
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.global _BB_IRQHandler_base
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.global _LLE_IRQHandler_base
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.align 1
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_vector_base:
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.option norvc;
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.word 0
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.word 0
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.word NMI_Handler /* NMI Handler */
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.word HardFault_Handler /* Hard Fault Handler */
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.word 0xF5F9BDA9 /* boot option, can't modify */
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.word Ecall_M_Mode_Handler /* 5 */
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.word 0
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.word 0
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.word Ecall_U_Mode_Handler /* 8 */
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.word Break_Point_Handler /* 9 */
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.word 0
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.word 0
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.word SysTick_Handler /* SysTick Handler */
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.word 0
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.word SW_Handler /* SW Handler */
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.word 0
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/* External Interrupts */
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.word unified_interrupt_entry /* TMR0 */
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.word unified_interrupt_entry /* GPIOA */
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.word unified_interrupt_entry /* GPIOB */
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.word unified_interrupt_entry /* SPI0 */
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_user_vector_base:
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.option norvc;
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.word unified_interrupt_entry /* BLEB */
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.word LLE_IRQHandler /* BLEL */
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.word unified_interrupt_entry /* USB */
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.word 0
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.word unified_interrupt_entry /* TMR1 */
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.word unified_interrupt_entry /* TMR2 */
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.word unified_interrupt_entry /* UART0 */
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.word unified_interrupt_entry /* UART1 */
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.word unified_interrupt_entry /* RTC */
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.word unified_interrupt_entry /* ADC */
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.word unified_interrupt_entry /* I2C */
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.word unified_interrupt_entry /* PWMX */
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.word unified_interrupt_entry /* TMR3 */
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.word unified_interrupt_entry /* UART2 */
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.word unified_interrupt_entry /* UART3 */
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.word unified_interrupt_entry /* WDOG_BAT */
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_real_user_vector_base:
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.option norvc;
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/* External Interrupts */
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.word TMR0_IRQHandler /* TMR0 */
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.word GPIOA_IRQHandler /* GPIOA */
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.word GPIOB_IRQHandler /* GPIOB */
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.word SPI0_IRQHandler /* SPI0 */
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_BB_IRQHandler_base:
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.word BB_IRQLibHandler /* BLEB BB_IRQHandler */
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_LLE_IRQHandler_base:
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.word LLE_IRQHandler /* BLEL LLE_IRQHandler */
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.word USB_IRQHandler /* USB */
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.word 0
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.word TMR1_IRQHandler /* TMR1 */
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.word TMR2_IRQHandler /* TMR2 */
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.word UART0_IRQHandler /* UART0 */
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.word UART1_IRQHandler /* UART1 */
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.word RTC_IRQHandler /* RTC */
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.word ADC_IRQHandler /* ADC */
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.word I2C_IRQHandler /* I2C */
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.word PWMX_IRQHandler /* PWMX */
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.word TMR3_IRQHandler /* TMR3 */
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.word UART2_IRQHandler /* UART2 */
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.word UART3_IRQHandler /* UART3 */
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.word WDOG_BAT_IRQHandler /* WDOG_BAT */
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.section .vector_handler, "ax", @progbits
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.weak NMI_Handler
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.weak HardFault_Handler
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.weak Ecall_M_Mode_Handler
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.weak Ecall_U_Mode_Handler
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.weak Break_Point_Handler
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.weak SysTick_Handler
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.weak SW_Handler
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.weak TMR0_IRQHandler
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.weak GPIOA_IRQHandler
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.weak GPIOB_IRQHandler
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.weak SPI0_IRQHandler
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.weak BB_IRQHandler
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.weak LLE_IRQHandler
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.weak BB_IRQLibHandler
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.weak USB_IRQHandler
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.weak TMR1_IRQHandler
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.weak TMR2_IRQHandler
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.weak UART0_IRQHandler
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.weak UART1_IRQHandler
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.weak RTC_IRQHandler
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.weak ADC_IRQHandler
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.weak I2C_IRQHandler
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.weak PWMX_IRQHandler
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.weak TMR3_IRQHandler
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.weak UART2_IRQHandler
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.weak UART3_IRQHandler
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.weak WDOG_BAT_IRQHandler
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NMI_Handler:
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HardFault_Handler:
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Ecall_M_Mode_Handler:
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Ecall_U_Mode_Handler:
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Break_Point_Handler:
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SysTick_Handler:
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SW_Handler:
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TMR0_IRQHandler:
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GPIOA_IRQHandler:
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GPIOB_IRQHandler:
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SPI0_IRQHandler:
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BB_IRQHandler:
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LLE_IRQHandler:
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BB_IRQLibHandler:
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USB_IRQHandler:
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TMR1_IRQHandler:
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TMR2_IRQHandler:
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UART0_IRQHandler:
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UART1_IRQHandler:
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RTC_IRQHandler:
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ADC_IRQHandler:
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I2C_IRQHandler:
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PWMX_IRQHandler:
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TMR3_IRQHandler:
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UART2_IRQHandler:
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UART3_IRQHandler:
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WDOG_BAT_IRQHandler:
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1:
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j 1b
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.section .handle_reset,"ax",@progbits
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.weak handle_reset
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.align 1
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handle_reset:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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1:
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la sp, _eusrstack
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/* Load highcode code section from flash to RAM */
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2:
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la a0, _highcode_lma
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la a1, _highcode_vma_start
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la a2, _highcode_vma_end
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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/* Load data section from flash to RAM */
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2:
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* 流水线控制位 & 动态预测控制位 */
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li t0, 0x1f
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csrw 0xbc0, t0
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/* 打开硬件压栈，关闭中断嵌套，在中断函数入口处再打开中断嵌套 */
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li t0, 0x01
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csrw 0x804, t0
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/* 使用机器模式，在freertos中打开中断 */
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li t0, 0x1800
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csrw mstatus, t0
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/* 配置系统异常及中断向量表，用户真正使用的向量表在统一入口 unified_interrupt_entry 中处理 */
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la t0, _vector_base
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ori t0, t0, 3
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csrw mtvec, t0
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la t0, main
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csrw mepc, t0
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mret
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.extern xISRStackTop
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.section .highcode.unified_interrupt_entry,"ax",@progbits
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.align 2
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.func
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unified_interrupt_entry:
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csrr a1, mcause
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slli a1, a1, 2
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la a0, _user_vector_base
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add a0, a0, a1
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lw a0, 0(a0) /* read isr functions addr from _vector_base. */
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#if ENABLE_INTERRUPT_NEST
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csrr t0, 0x804 /* justice whether it's in interrupt nesting. */
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andi t1, t0, 0x02
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bnez t1, interrupt_nesting /* if it's not zero, it's in interrupt nesting. */
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#endif
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csrw mscratch, sp
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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#if ENABLE_INTERRUPT_NEST
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csrs 0x804, 0x02 /* enable interrupt nests. */
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#endif
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jalr x1, 0(a0)
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#if ENABLE_INTERRUPT_NEST
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csrc mstatus, 8 /* disable interrupt in machine mode. */
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nop /* wait for 3 grade pipeline. */
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nop
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nop
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csrc 0x804, 0x02 /* disable interrupt nests. */
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nop
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#endif
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csrr sp, mscratch /* resume sp from mscratch. */
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mret
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#if ENABLE_INTERRUPT_NEST
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interrupt_nesting:
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jalr x1, 0(a0) /* if it's in interrupt nesting, don't need to change sp. */
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mret
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#endif
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.endfunc
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