306 lines
		
	
	
	
		
			7.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			306 lines
		
	
	
	
		
			7.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /********************************** (C) COPYRIGHT  *******************************
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|  * File Name          : core_riscv.c
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|  * Author             : WCH
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|  * Version            : V1.1.0
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|  * Date               : 2021/06/06
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|  * Description        : RISC-V Core Peripheral Access Layer Source File
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|  *********************************************************************************
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|  * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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|  * Attention: This software (modified or not) and binary are used for 
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|  * microcontroller manufactured by Nanjing Qinheng Microelectronics.
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|  *******************************************************************************/
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| #include <stdint.h>
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| 
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| /* define compiler specific symbols */
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| #if defined ( __CC_ARM   )
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|   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
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|   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
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| 
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| #elif defined ( __ICCARM__ )
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|   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
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|   #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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| 
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| #elif defined   (  __GNUC__  )
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|   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
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|   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
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| 
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| #elif defined   (  __TASKING__  )
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|   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
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|   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
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| 
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| #endif
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| 
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| 
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| 
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| /*********************************************************************
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|  * @fn      __get_MSTATUS
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|  *
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|  * @brief   Return the Machine Status Register
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|  *
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|  * @return  mstatus value
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|  */
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| uint32_t __get_MSTATUS(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MSTATUS
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|  *
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|  * @brief   Set the Machine Status Register
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|  *
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|  * @param   value  - set mstatus value
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|  *
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|  * @return  none
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|  */
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| void __set_MSTATUS(uint32_t value)
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| {
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|   __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MISA
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|  *
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|  * @brief   Return the Machine ISA Register
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|  *
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|  * @return  misa value
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|  */
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| uint32_t __get_MISA(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MISA
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|  *
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|  * @brief   Set the Machine ISA Register
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|  *
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|  * @param   value  - set misa value
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|  *
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|  * @return  none
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|  */
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| void __set_MISA(uint32_t value)
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| {
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|   __ASM volatile ("csrw misa, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MTVEC
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|  *
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|  * @brief   Return the Machine Trap-Vector Base-Address Register
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|  *
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|  * @return  mtvec value
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|  */
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| uint32_t __get_MTVEC(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MTVEC
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|  *
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|  * @brief   Set the Machine Trap-Vector Base-Address Register
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|  *
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|  * @param   value  - set mtvec value
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|  *
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|  * @return  none
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|  */
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| void __set_MTVEC(uint32_t value)
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| {
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|   __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MSCRATCH
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|  *
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|  * @brief   Return the Machine Seratch Register
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|  *
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|  * @return  mscratch value
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|  */
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| uint32_t __get_MSCRATCH(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MSCRATCH
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|  *
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|  * @brief   Set the Machine Seratch Register
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|  *
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|  * @param   value  - set mscratch value
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|  *
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|  * @return  none
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|  */
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| void __set_MSCRATCH(uint32_t value)
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| {
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|   __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MEPC
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|  *
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|  * @brief   Return the Machine Exception Program Register
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|  *
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|  * @return  mepc value
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|  */
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| uint32_t __get_MEPC(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MEPC
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|  *
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|  * @brief   Set the Machine Exception Program Register
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|  *
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|  * @return  mepc value
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|  */
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| void __set_MEPC(uint32_t value)
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| {
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|   __ASM volatile ("csrw mepc, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MCAUSE
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|  *
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|  * @brief   Return the Machine Cause Register
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|  *
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|  * @return  mcause value
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|  */
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| uint32_t __get_MCAUSE(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MEPC
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|  *
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|  * @brief   Set the Machine Cause Register
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|  *
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|  * @return  mcause value
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|  */
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| void __set_MCAUSE(uint32_t value)
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| {
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|   __ASM volatile ("csrw mcause, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MTVAL
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|  *
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|  * @brief   Return the Machine Trap Value Register
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|  *
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|  * @return  mtval value
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|  */
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| uint32_t __get_MTVAL(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __set_MTVAL
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|  *
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|  * @brief   Set the Machine Trap Value Register
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|  *
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|  * @return  mtval value
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|  */
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| void __set_MTVAL(uint32_t value)
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| {
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|   __ASM volatile ("csrw mtval, %0" : : "r" (value) );
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MVENDORID
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|  *
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|  * @brief   Return Vendor ID Register
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|  *
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|  * @return  mvendorid value
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|  */
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| uint32_t __get_MVENDORID(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MARCHID
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|  *
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|  * @brief   Return Machine Architecture ID Register
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|  *
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|  * @return  marchid value
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|  */
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| uint32_t __get_MARCHID(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MIMPID
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|  *
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|  * @brief   Return Machine Implementation ID Register
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|  *
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|  * @return  mimpid value
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|  */
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| uint32_t __get_MIMPID(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_MHARTID
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|  *
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|  * @brief   Return Hart ID Register
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|  *
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|  * @return  mhartid value
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|  */
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| uint32_t __get_MHARTID(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
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|   return (result);
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| }
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| 
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| /*********************************************************************
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|  * @fn      __get_SP
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|  *
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|  * @brief   Return SP Register
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|  *
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|  * @return  SP value
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|  */
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| uint32_t __get_SP(void)
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| {
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|   uint32_t result;
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| 
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|   __ASM volatile ( "mv %0," "sp" : "=r"(result) : );
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|   return (result);
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| }
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| 
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